The present invention relates to a semiconductor memory device and a test system and, mainly, a technique effective for use in a technique of a probing test on a dynamic RAM (Random Access Memory).
An example of a memory integrated circuit capable of realizing the functions of a timing margin test, a voltage margin test, and detection of abnormal current by built-in functions is disclosed in the publication of Japanese Unexamined Patent Application No. Hei 8(1996)-315598. A memory integrated circuit of the publication has therein a built-in test function (BIST) unit for generating a memory test signal and various control signals, a timing generation circuit and a voltage generation circuit which are controlled by an output signal of the sequence unit, and a current sensor for detecting an abnormal current, in which a current-to-voltage converting circuit and an analog-to-digital converting circuit are connected in series.
In the memory integrated circuit having therein, in addition to the test built-in function unit, timing generation circuit, a voltage generation circuit, a current-to-voltage converting circuit, and a current sensor, the scale of the test circuit occupying the memory integrated circuit is large; and, moreover, since the test circuit is used only at the time of a test, there are problems in that the chip size is enlarged, in terms of storage bits as the inherent function of the memory integrated circuit, and the current consumption is increased. The publication indicates that the problems of the circuit scale and the like are solved by a relative decrease in the test circuit area in association with a finer circuit and an increase in the capacity of the memory. However, it is not realistic to allow a large-scale test circuit, as described above, to be built in a general memory, such as dynamic RAM having storage capacity of about 64 Mbits or 256 Mbits as practically used at present.
The throughput of a probing test on a dynamic RAM or the like is determined by test time per chip and the number of chips (the number of chips simultaneous measured). The number of chips simultaneous measured is, however, under constraints of each of various hardware. For example, the number of bonding pads of a synchronous DRAM (Dynamic RAM) of 64 Mbits is equal to at least 60 to 70 which is the sum of about 54 of external terminals except for NC pins and special pads used for a probing test.
On the other hand, the maximum number of needles of a probe card to be electrically connected to the bonding pads is about 1,000 to 1,500. Accordingly, the maximum number of devices to be measured simultaneously is about 20. When the number of devices to be simultaneously measured increases, the number of generating times of signals, the number of comparators, and the number of power units on the tester side are also increased, thereby raising the price of the tester. Further, it causes problems such that the cost of a multi-needle probe card increases and the life becomes shorter. Consequently, it is not easy to increase the number of devices to be simultaneously measured.
The inventors of the present invention have therefore examined solution of the problems while minimizing the number of needle pads used for a probing test. In association with the increase in the diameter of a wafer in recent years, the number of memory chips obtained is conspicuously increasing. It is estimated that the number of chips to be simultaneously measured has to be increased more and more. As methods of decreasing the number of needle pads at the time of a probing test, reduction in the number of power source needle pads, reduction in the number of data input/output pads, reduction in the number of address input pads, and reduction in the number of clock input pads can be mentioned. The power source pads can be eliminated by connecting the power source in a memory chip except for a pair of VCC and VSS as long as the characteristics can be maintained. If the address input pads and clock input pads are eliminated, however, tests of reading and writing data from/to a memory by designating an address cannot be conducted. A method of designating memory access patterns such as matching patterns by a simple control from the outside and generating them on the inside may be considered. It is, however, estimated that the logic in the chip becomes large and complicated, it causes an increase in chip size and deterioration in yield, and the method does not contribute to reduction in cost as a total.
An object of the invention is, therefore, to provide a semiconductor memory device and a test system capable of conducting a memory test with a simple configuration. Another object of the invention is to provide a semiconductor memory device and a test system capable of conducting a probing test with a smaller number of needle pads. Further another object of the invention is to provide a semiconductor memory device and a test system capable of simultaneously measuring the increased number of chips. The above and other objects and novel features of the invention will become apparent from the description of the specification and the attached drawings.
A representative technique of the present invention disclosed in the specification will be briefly described as follows. A memory circuit having a memory cell array in which a plurality of memory cells are provided at intersection points of a plurality of word lines and a plurality of bit line pairs and a peripheral circuit for performing an operation of selecting an address is provided with: an arithmetic unit which is also called an arithmetic circuit, a computing unit or a computing circuit below for generating an address signal for a test on the memory circuit; a packet decoder for designating the kind of operation on the arithmetic unit; and an input circuit for supplying a test signal comprising a plurality of bits for designating a test operation to the packet decoder.